CBSE NET July 2016 PAPER II
Q. In a Positive edge triggered JK flip-flop, if J and K both are high then the output will be _______ on the rising edge of the clock.
(A) No change
(B) Set
(C) Reset
(D) Toggle
Ans :- (D)
Explanation:-
State table of JK Flip Flop –
|
J
|
K
|
OUTPUT
|
|
0
|
0
|
No change
|
|
0
|
1
|
0
|
|
1
|
0
|
1
|
|
1
|
1
|
Toggle
|
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