Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.

1.The control unit consists of 2 decoders, 1 sequence counter, number of control logic gates.

2. The instruction in IR is divide into 3 parts : 15th bit to a flip-flop (FF) called I, Operation code, and bits 0 to 11. The Op-code is decoded using 3*8 decoder (D₀to D₇). Bits 0 to 11 are applied to the control logic gates. The output of a 4-bit sequence counter are decoded into 16 timing signals(T₀ to T₁₅).

3.The SC responds to the positive transition of the clock. Initially CLR I/ P is active, in 1st positive transition SC = 0, timing signal T₀
is active as the output of the decoder. This in turn triggers those registers whose control inputs are connected to T0. SC is incremented and the timing signals T₀,T₁, T₂, T₃…. are created. This continues unless SC is cleared. We can clear the SC with decoder output D₃ active, denoted as : D₃T₄ : SC←0

4.Output D3 from the operation decoder becomes active at the end of T2.When T4 is active, the output of AND gate that implements the control function D3T4 becomes active. This signal is applied to CLR input of SC.

5.Example of register transfer : T0 : AR  PC (Activities in T0will be, Content of PC placed on bus, S2S1S0 = 010, LD of AR is active, transfer occurs at the end of positive transition, T0 is .inactive, T1 gets active).

6.Timing control is generated by 4-bit sequence counter and 4 × 16 decoder. The SC can be incremented or cleared. T0, T1, T2, T3,T4, T0, ………
For example :
Assume : At time T4, SC is cleared to 0 if decoder output D3 is active.D3T4 : SC ← 0

Timing diagram :