In an instruction format, there are 16 bits in an instruction word. Bit 0 to 11 convey the address of the memory location for memory related instructions. For non memory instructions these bits convey various register or I/O operations. Bits 12 to 14 show the various basic memory operations such asADD, AND, LDA etc. Bit 15 shows if the memory is accessed directly or indirectly. For such an instruction format draw block diagram of the control unit of a computer and briefly explain how an instruction will be decoded and executed, by this control unit.

1.Consider the instruction code format shown in image (a). It consists of a 3-bit operation code, a 12-bit address, and an indirect address mode bit designated by I.

2. The mode bit is 0 for a direct address and 1 for an indirect address.

3.A direct address instruction is shown in image (b). It is placed in address 22 in memory. The I bit is 0, so the instruction is recognized as a direct address instruction.

4.The opcode specifies an ADD instruction, and the address part is the binary equivalent of 457.

5.The control finds the operand in memory at address 457 and adds it to the content of AC.

6.The instruction in address 35 shown in image (c) has a mode bit I = 1. Therefore, it is recognized as an indirect address instruction.

7.The address part is the binary equivalent of 300. The control goes to address 300 to find the address of the operand.

8.The address of the operand in this case is 1350. The operand found in address 1350 is then added to the content of AC.

9.The indirect address instruction needs two references to memory to fetch an operand.

Instruction will be decoded and executed by this control unit :

1.Control unit consists of :
i. Instruction register
ii. Number of control logic gates
iii. Two decoders
iv. 4-bit sequence counter

2.An instruction read from memory is placed in the Instruction Register (IR).

3.The instruction register is divided into three parts : the I bit, operation code, and address part.

4.First 12-bits (0 – 11) are applied to the control logic gates.

5.The operation code bits (12 – 14) are decoded with a 3 × 8 decoder.

6.The eight outputs (D0 through D7) from a decoder go to the control logic gates to perform specific operation.

7.Last bit 15 is transferred to a I flip-flop designated by symbol I.

8.The 4-bit Sequence Counter (SC) can count in binary from 0 through15.

9.The counter output is decoded into 16 timing pulses T0 through T15.

10.The sequence counter can be incremented by INR input or clear by CLR input synchronously.