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Explain 2D, 2 12 D memory organization. Memory OR Write short note on organization of 2D and 2.5D memory organization.

2D organization :

  1. The cells are organized in the form of a two-dimensional array with rows and columns.
  2. Each row refers to word line. For 4-bit per word memory, 4 cells are interconnected to a word line. Each column in the array refers to a bit line.
  1. The Memory Address Register (MAR) holds the address of the location where read/write operation is executed. In image, MAR has 4-bit lines.
  2. The content of MAR is decoded by an address decoder on the chip to activate each word line.
  3. The cells in each column are connected to a sense/write circuit by two bit lines. Two bit lines are complement to each other.
  4. The sense/write circuits are activated by the Chip Select (CS) lines. The sense/write circuits are connected to the data lines of the chip.
  5. During a read operation, these circuits sense or read the information stored in the cells selected by a word line and transmit this information to the data lines.
  6. During a write operation, the sense/write circuits receive or write input information from the data lines and store it in the selected cells.

2.5D organization :

  1. In 2.5D organization there exists a segment.
  2. The content of MAR is divided into two parts–x and y number of bits.
  3. The number of segments S is equal to 2y.
  4. X = 2x drive lines are fed into the cell array and y number of bits decode one bit line out of S lines fed into a segment of the array. In total, there are Sb number of bit lines for a b bit per word memory.
  5. Thus for any given address in the MAR, the column decoder decodes b out of Sb bit lines by using the y bits of the MAR while a particular word line is activated by using the x bits.
  6. Thus only the b numbers of bits in the array are accessed by enabling the word line and b number of bit lines simultaneously.
  7. Though 2.5D organized memory may need lesser chip decoding logic, it suffers from one drawback. With high density chips, a simple failure, such as external pin connection op

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